
Principal Engineer, VLSI Design Engineering
Global-Talent-Exchange
Required Skills:
Verilog
RTL Design
Signoff Timing Analysis
Clock Domain Crossing
RDC
Verilog
RTL design
Timing Analysis
Clock Domain Crossing
RDC
SOC/ASIC development
NAND flash technology
Job Description
Looking for an experienced engineer to join a team working on the Logic Design of 3D NAND flash memory. As part of the design team, the individual will be responsible for Logic design development and ownership of the RTL modules. The individual has to exhibit a highly innovative mindset and come up with the solutions for the next technology.
Essential Duties And Responsibilities
- Understand the NAND architecture and collaborate with other Core/Analog design groups.
- Drive the design activities and responsible for design of the RTL modules.
- Timing Closure of the Logic modules.
- Create the SVA check specs.
- Work with verification team on the creating and updating test plans.
- With the cross-functional teams on implementing the new modes.
- Work with the BUs to come up with the effective solution based on customer requirements.
- Develop the verification for the new modes implemented. Simulate and debug the RTL using the industry standard tools.
Qualifications
- Experience of 9-12 years in SOC/ASIC development. Knowledge of NAND flash technology is an added advantage.
- Bachelor's/Master's degree in the Electrical Engineering/Microelectronics.
- Should have contributed in the Design for at least 1 taped-out project.
- Proficient in Verilog language and RTL design.
- Proficient in Timing Analysis.
- Expertise in Clock Domain Crossing(CDC) and RDC.
- Detail-oriented candidate who can work with cross-functional teams and the verification teams.
- Strong problem-solving skills.
- Should have excellent communication written, oral and presentation skills.
- Should demonstrate leadership skills and drive the innovation activities with the team.
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