Experience – 5+ Years in Layout Design, SRAM, Memory Layout experience is preferred.

Qualifications for this position include: 

• Hands on experience and proficiency in EDA tools (Cadence Virtuoso Layout and Schematic Editor, Calibre etc.) 
• Excellent circuit design, layout, schematic, and verification skills including DRC, LVS and circuit simulation (hspice) 
• Good knowledge of semiconductor device physics & operation and parametric measurements
• Knowledge of Memory Array design architectures, fab processes, and failure modes is preferred
• Excellent problem solving and strong interpersonal skills 
• Willingness to learn new skills and explore unfamiliar concepts 
• Proficiency in Perl, Skill code and UNIX shell scripting languages is desired, but not required