Skills Required

• 10-15years of relevant experience in ASIC Physical Verification
• Good understanding of overall design Flow from RTL to GDS.
• Hands on Experience on Physical Verification closure of full chip & Hierarchical Designs
• Hands on DRC & LVS Experience on Lower node Technologies with Synopsys/Siemens Tools
• Good knowledge on PnR flow
• Knowledge on Perl / TCL / Python scripting language
• Experience on multi voltage designs
• Good understanding of all Phases of Physical Design (PnR/STA/PV/IR)

Responsibilities

• Responsible for Block/ Chip Tile PV closure to achieve the best PPA
• DRC & LVS closure for Block and Full Chip for complex hierarchical Designs in 5nm/3nm nodes
• Interaction with IR, IP , ESD & PD teams for Physical Verification Convergence & Resolving Conflicts
• Able to work on multiple blocks at same time with minimal supervision
• Responsible for Full Chip LVS & DRC closure
• Responsible for Analog integration closure for all IP"s used in SOC 
• Interactions with Foundry team for Full chip Tapeout