Unique Opportunities

• Complete ownership of verification and end to end analysis of sophisticated full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as HBM,DDR4,LPDDR4,DDR5 and LPDDR5 that can operate at high speeds of up to 6400MT/s.
• Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design.
• Work on multi-functional tasks that can widen your skills.

Responsibilities:

• Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes.
• Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon full chip designs.
• Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features.
• Participate in developing verification methodology and verification environments for sophisticated products.
• Co-work with international colleagues on developing new verification flows to take on the challenges in design.
• Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.

Core Requirements

• Good communication skills and ability to work well in a team
• Guide new team members and energetic engineers in the team
• Analytical capability for complex CMOS and/or gate level circuit designs
• Proficient with either SPICE and/or Verilog simulations

Qualifications & Skills

• Experience in SystemVerilog, PLI coding, Gate Level Sims
• Experience in UVM Test Bench
• Experience in DRAM, SRAM or other memory related fields
• Experience in AMS verification and co-sim

Education

Bachelors or Post Graduate Degree in Electronics Engineering or related

engineering field required