ASIC Design Verification Engineer – PCIe

ASIC Design Verification Engineer – PCIe

• 8+ years of experience in ASIC/SOC/IP/Block-level functional verification.
• Strong command over SystemVerilog, UVM, and advanced verification methodologies.
• Deep experience with PCIe protocol (Gen3/Gen4/Gen5/Gen6) verification is mandatory.
• Hands-on expertise in developing and debugging testbenches for complex protocols such as PCIe, DDR, Ethernet, USB, or NVMe (PCIe required).
• Proficient in using industry-standard simulators such as Questa, VCS, or ModelSim.
• Strong debugging skills using waveform viewers like DVE, SimVision, or Verdi.
• Experience with functional and code coverage closure.
• Proficiency in scripting languages: Python, Perl, or TCL.