Analog Designer

Role Overview

The I/O Pad Ring Team is seeking a candidate to perform I/O pad ring physical verification duties and methodology improvements on multiple exciting products. The role involves working on interfaces like PLL, DDR, GDDR, USB, HDMI, PCIE, and GPIO. The team is crucial to the success of our organization as a cutting-edge company.

Responsibilities

• Assemble macros/IPs/RDL into an I/O pad ring database and run verification tools to identify integration issues.
• Communicate with IP owners to resolve issues.
• Conduct physical verification on designs with up to 200M devices.
• Deliver necessary waivers and documentation to SoC teams.
• Facilitate ESD and design reviews for third-party IPs and I/O ring.

Preferred Skills

• Strong understanding of physical verification checks and ability to debug and resolve issues.
• Knowledge of chip level integration and Electrical Static Discharge concepts.
• Experience with Mentor Calibre and Synopsys tools.
• Perl programming, TCL, SVRF, TVF programming is advantageous.
• IP layout design experience and exposure to Cadence is a plus.

Education

• Degree in Electrical/Computer/Biomedical/Mechanical Engineering or related field.

Our organization is an equal opportunity employer and encourages applications from all qualified candidates.