
Digital ASIC Design Engineer
Global-Talent-Exchange
Required Skills:
RTL Design
Verilog
SystemVerilog
VHDL
Eda Tools Questasim
Uvm Level Verification
RTL design
Verilog
SystemVerilog
VHDL
EDA tools
UVM verification
About This Vacancy
As Digital ASIC Design Engineer, you will play a key role in the design, verification and implementation of cutting-edge digital ASIC's.
Your Responsibilities
- Design and develop RTL for ASIC blocks and subsystems.
- Contribute to documentation, design reviews, and knowledge sharing.
- Optimize for performance and power.
- Collaborate with verification engineers.
What We Expect From You
- Master's degree in Electronics or a related field.
- At least 5 years experience in RTL design using Verilog/SystemVerilog or VHDL.
- Proficiency with EDA tools (Synopsys, Cadence, or Mentor).
- Experience with UVM verification methodology is a plus.
- Fluent in English.
What You Can Expect From Us
Our organization is an international high-tech consultancy company that brings expertise to its clients in order to support them with the realization of their technological challenges. We offer you a challenging and stimulating work environment in which you can be the director of your own career. Fun and engagement are meaningful parts of our culture.
About Company

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