Ingénieur conception ASIC H/F

Job Description

As a digital ASIC design engineer, you will work on complex projects in a secure environment adhering to certain development standards.

You will be responsible for:

• Designing RTL frontend hardware
• Writing specifications
• Developing RTL code (Verilog and VHDL)
• Simulation
• Design verification in SystemVerilog (especially with UVM methodologies)
• Implementing tests developed in C
• Configuration management with SVN or Git
• Adhering to internal design flow standards

Required Profile

• Engineering degree or equivalent in electronics, microelectronics, or embedded systems
• Minimum 2 years of experience in ASIC verification
• Proficiency in SystemVerilog, Verilog/VHDL
• Expertise in UVM methodologies and knowledge of PSS standards
• Familiarity with verification tools (Cadence, Spyglass, JasperGold)
• Autonomy, rigor, and ability to work in a team

Benefits

• 10 days of RTT per year
• Meal allowance or restaurant voucher almost fully covered
• Family Health Insurance
• Time Savings Account
• Profit sharing and incentives
• Referral bonus of 1000 or 1500 €
• Vacation bonus
• Transport bonus