Erfaren FPGA/ASIC Designingeniør

Global-Talent-Exchange

Denmark
Full time
3 Yrs
Job Openings: 1

Required Skills:

FPGA

Custom Asic

VHDL

Verilog

RTL Coding

Synthesis

Signoff Timing Analysis

Digital Designer

FPGA

ASIC

VHDL

Verilog

RTL coding

Synthesis

Timing analysis

Digital design

The position is posted in Danish as there is a requirement to communicate in Danish for an upcoming task.

About Us:

Our organization is a leading design house specializing in efficient solutions for the data and telecommunications industry. We focus on FPGA/ASIC development and embedded software with expertise in areas such as packet switches, 800G/1.6T optical transport, 5G/6G wireless systems, and security solutions. We are dedicated to advancing communication technologies and typically work with the latest chips for market-leading international clients.

Job Description:

We are expanding our on-site team and are currently seeking an experienced digital design engineer to take a central role in our FPGA projects.

The ideal candidate has more than 10 years of experience in digital design and experience with complex projects in small to medium-sized teams. The position is suitable for someone who thrives in an independent role or has ambitions to lead and coach a small team.

As the job involves collaboration with both large international and smaller local clients, proficiency in English and Danish at a conversational level is required.

We have a very flat organization with a balanced age distribution, where you will have significant influence over tasks and schedules for your projects.

Responsibilities:

  • Take a central role in the design, implementation, and verification of FPGA and ASIC designs.
  • Independently drive RTL coding, synthesis, and timing analysis.
  • Collaborate with other engineers and, where relevant, take leadership in design, debugging, and problem-solving.
  • Work with international teams to ensure successful digital designs for some of the world's largest companies.

Qualifications:

  • Minimum 3 years of experience as an ASIC/FPGA design engineer focusing on complex digital designs in VHDL or Verilog.
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Solid understanding of ASIC/FPGA design.
  • Experience with synthesis, place and route, and timing analysis of high-speed or low-power designs.
  • In-depth knowledge of principles and concepts in digital design.
  • Familiarity with standard tools for ASIC/FPGA design and verification.
  • Strong communication and collaboration skills.

If you are an experienced and dedicated digital design engineer with a passion for coaching and leadership - or an independent profile seeking a challenging and rewarding position - we encourage you to apply. Join our organization and contribute to projects in digital communication.

About Company

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