Design Verification Engineer

Senior Verification Engineer

We are seeking a Senior Verification Engineer with expertise in Digital Design Verification and High-Speed Communication Protocols. The role is based in Austin and involves working with UVM and DSP technologies.

Responsibilities:

• Conduct digital design verification for high-speed communication protocols.
• Utilize VLSI verification flows, concepts, and methodologies.
• Complete full block/system verification cycles through to tape-out.
• Apply industry-standard verification methodologies such as UVM and SystemVerilog.
• Work with high-speed communication protocols including Ethernet, SerDes, and PCIe.

Qualifications:

• 5+ years of experience in digital design verification.
• Extensive knowledge of VLSI verification flows.
• Experience with UVM, SystemVerilog, and high-speed communication protocols.
• Driven and enthusiastic individual ready for a new challenge in a dynamic environment.

If you are interested in this opportunity, please apply directly for immediate consideration.