ASIC Design Engineer, Clocks

Job Description

The GPU clocks group is seeking a skilled Senior ASIC Design Engineer. The team is responsible for all aspects of GPU clocking, collaborating with frontend and backend teams to meet chip requirements and physical constraints. The group architects, designs, and validates clocks RTL, supporting features across various product lines.

Responsibilities

• Collaborate with architects, ASIC designers, and verification engineers to design high frequency and low power clocks.
• Engage with multiple teams to design GPU clocks that satisfy architectural constraints.
• Enhance in-house flows to ensure quality of clocks RTL and netlist.
• Deliver clock information to SOC verification, timing, and DFT teams.
• Use Perl/Python to improve team productivity.
• Collaborate with software and silicon solution teams to debug GPU clock silicon bugs.

Qualifications

• BS or MS in EE or equivalent experience.
• 2+ years of relevant work experience.
• Experience in RTL design (Verilog), verification, and logic synthesis.
• Strong coding skills in Perl, Python, or other scripting languages.
• Understanding of sub-micron silicon issues is a plus.
• Knowledge of backend flows and DFT is a plus.
• Experience in implementing on-chip clocking networks is desirable.
• Excellent analytical and problem-solving skills.
• Fluent English and excellent communication skills.
• Good teamwork spirit and cooperation skills.