Application Specific Integrated Circuit Design Engineer

Global-Talent-Exchange

Germany
Full time
5 - 8 Yrs
Job Openings: 1

Required Skills:

HDL Designer

SystemVerilog

Simulation Tools

Cadence Xcelium

O Timing Constraints

Synthesis

Functional Verification

Systemverilog Uvm

HDL design

SystemVerilog

simulation tools

Cadence XCELIUM

timing constraints

synthesis

functional verification

UVM

SystemVerilog assertions

Job Description

We are seeking a highly skilled and experienced Senior Digital / RTL Design Engineer to join our system design team. This role offers the opportunity to work on cutting-edge network solutions and protocols, contributing to the development of high-quality, high-performance digital designs. As part of our team, you will play a key role in the design process, from specification to implementation, while collaborating with cross-functional teams to ensure successful product delivery.

Responsibilities

  • Analyse and interpret complex design specifications or industry standards, translating them into detailed microarchitecture specifications and requirements.
  • Develop and maintain complex digital IPs at the RTL level based on microarchitecture specifications, taking ownership of IP blocks or sub-blocks.
  • Support digital IP blocks throughout their lifecycle, from design and verification to tape-out and bring-up.
  • Collaborate with the functional verification team to identify and debug errors.
  • Create and contribute to internal and customer-facing product specification documentation.
  • Work closely with architecture, verification, backend, and firmware teams to ensure seamless integration and functionality.
  • Participate in cross-functional groups to support timely and successful product releases.

Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering, Physics, Computer Engineering, Information Technology, or a related field with a focus on hardware design.
  • Minimum of 5 years of professional experience, including internships.
  • Proficiency in HDL design, preferably using SystemVerilog.
  • Experience with simulation tools such as Cadence XCELIUM or comparable simulators.
  • Basic knowledge of timing constraints and synthesis is advantageous.
  • Familiarity with functional verification (UVM) and SystemVerilog assertions is a plus.
  • Excellent written and verbal communication skills in English; knowledge of German is a plus.

If you are passionate about digital design and eager to contribute to innovative projects in a collaborative environment, we encourage you to apply for this exciting opportunity.

About Company

Global-Talent-Exchange
https://globaltalex.com/
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10-20 Employees
Information Technology & Services