
Senior Physical Design Engineer
Global-Talent-Exchange
Required Skills:
Floorplanning
Synthesis
Place & Route
Timing Closure
Eda Tools Questasim
RTL Design
Verilog
SystemVerilog
Cmos Bulk Technologies
Familiarity With Scripting Using Tcl
floorplanning
synthesis
place & route
timing closure
EDA tools
RTL design
Verilog
SystemVerilog
CMOS technologies
TCL scripting
Senior Physical Design Engineer - Mannheim
Our client is seeking a highly skilled Senior Physical Design Engineer to work on cutting-edge interface IP and test chip development. This role offers hands-on exposure to the full RTL-to-GDSII flow and the chance to tackle complex challenges in modern CMOS technologies.
What you’ll do:
As a Senior Physical Design Engineer, you will:
- Lead and support the complete physical implementation and verification flow, including floorplanning, synthesis, place & route (PnR), and timing closure for advanced interface IP such as high-speed SerDes and interconnects.
- Collaborate with analog and digital design teams to ensure seamless integration of IP into complex systems.
- Identify and implement optimal solutions when porting IP to new technology nodes or metal stacks.
- Enhance internal design methodology by testing the latest EDA tool capabilities and integrating improvements into the development flow.
What they're looking for:
- Proven experience across the full physical design flow: floorplanning, synthesis, PnR, and timing closure
- Hands-on experience with EDA tools from major vendors
- Strong fundamentals in RTL design (Verilog or SystemVerilog)
- Knowledge of modern CMOS technologies
- Scripting experience, preferably in TCL
This is an excellent opportunity for a Senior Physical Design Engineer who wants to expand their expertise, contribute to challenging projects, and make a direct impact on the development of high-performance IP and next-generation chiplets.
About Company

Send me jobs like this
This one's a match? We'll send more your way
Similar Jobs

STA & RTL Design Engineer
Micron Technology
Bangalore Rural, India
Full time
8 - 20 Years

Staff Design Engineer - RTL Firmware
Micron Technology
Bangalore Rural, India
Full time
8 - 20 Years

Staff Engineer – ASIC Digital Design (PHY IP)
Micron Technology
Bangalore Rural, India
Full time
8 - 20 Years

ASIC Design Verification Engineer – PCIe
Cyient
Bangalore Rural, India
Full time
8 - 15 Years

Digital Hardware/FPGA Engineer II
Global-Talent-Exchange
Abu Dhabi Municipality, United Arab Emirates
Full time
5 - 7 Years

Elektronik Hardware Entwickler:in für Embedded Systeme (M/W/D)*
Global-Talent-Exchange
Wels, Austria
Full time
3 - 5 Years

Hardware-Entwickler:in (all genders)
Global-Talent-Exchange
Austria
Full time
2 - 5 Years

Design Verification Engineer
Global-Talent-Exchange
Bangalore Rural, Australia
Full time
2 - 12 Years

Design Verification Engineer -- Bangalore
Global-Talent-Exchange
Australia
Full time
2 - 12 Years

ASIC Test Engineer | Semiconductors
Global-Talent-Exchange
Belgium
Full time
7 Years