Layout Engineer

Job Description

Responsible for understanding and applying all necessary layout guidelines, new process rules, and other technical requirements for quality layout. Schedule timeline and layout floor-planning. Complete quality layout and verification within the planned schedule. Quickly adapt to new methodologies, be open to new ideas, and communicate well with others in the team.

Skill Set / Requirements

• Bachelor's degree in Electronics Engineering with a minimum of 2 years of layout experience.
• Experience in standard cells or full custom and/or analog layout design and physical verifications including LVS, DRC, ERC, Antenna, Electro Migration (EMIR) in Finfet, CMOS process.
• Good experience in floor-planning, hierarchy layout, and chip integration.
• Experienced in Cadence Layout tools VIRTUOSO (XL, VXL, or EXL), and CALIBRE verification tools.
• Good understanding of Latch-up and ESD in CMOS process and implementation for IO layout design.
• Knowledge of Script Programming and SKILL Programming is a plus.
• Self-reliant, with the ability to work independently as well as in a team.
• Strong layout knowledge in advanced processes, e.g., 5nm, 3nm, 2nm.