Design Verification Engineer - Lead

Role: Lead – SoC/Sub-System Design Verification

Location is Sunnyvale CA.

About the Role

We are seeking an experienced Design Verification Lead to drive SoC-level verification strategy, lead high‑performing teams, and ensure first‑time‑right silicon. This role requires deep technical expertise, strong leadership, and the ability to influence cross‑functional teams while working in a fast‑paced environment.

Your Responsibilities

• Lead an SoC Verification team, owning verification of the SoC and integration of its subsystems and flows.
• Define, drive, and execute verification strategy, including test plans, requirements, environments, tools, and methodologies.
• Review architecture specifications; collaborate with architects and RTL designers to assess the impact of architectural changes.
• Create, develop, and maintain UVM/SystemVerilog‑based testbenches for block, subsystem/cluster, and full‑chip verification.
• Drive functional coverage, simulation strategies, emulation plans, and formal verification usage where applicable.
• Perform and guide Gate‑Level Simulation (GLS) bring‑up, timing simulations, and signoff activities.
• Debug complex SoC‑level issues across simulation, emulation, and silicon‑like environments.
• Mentor and coach team members, fostering technical growth and excellence across the team.
• Collaborate with cross‑functional stakeholders to deliver robust SoC verification solutions and ensure on‑schedule, high‑quality deliverables.

Your Profile

• 12+ years of experience in SoC design and verification.
• Strong expertise in UVM, UPF, and protocol VIPs.
• Proven ability to define and execute verification strategies at SoC and subsystem levels.
• Hands‑on experience with AMBA protocols (AXI, AHB, APB) and at least one high‑speed or memory protocol.
• Proficient in SystemVerilog, VHDL, Python, and TCL scripting.
• Deep understanding of functional coverage, constrained random verification, simulation, emulation, and formal methods.
• Experience participating in or driving architecture reviews and responding to design/architecture changes.
• Strong debugging skills with the ability to work independently in fast‑paced environments.
• Demonstrated ability to lead teams, influence stakeholders, and deliver strategic technical solutions.
• Master’s degree in Electrical Engineering, Computer Science, or a related field.

Nice to Have

• Experience with performance verification.
• Hands‑on exposure to formal verification methodologies.

The base compensation range for this role in the posted location is $86,900 to $203,800 / year.

In addition to base salary, this role may be eligible for additional compensation such as variable incentives, bonuses, or commissions, depending on the position and applicable laws.

Capgemini offers a comprehensive, non-negotiable benefits package to all regular, full-time employees. In the U.S. and Canada, available benefits are determined by local policy and eligibility and may include:

• Paid time off based on employee grade (A-F), defined by policy: Vacation: 12-25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave
• Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)
• Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)
• Life and disability insurance
• Employee assistance programs
• Other benefits as provided by local policy and eligibility

Important Notice: Compensation (including bonuses, commissions, or other forms of incentive pay) is not considered earned, vested, or payable until it becomes due under the terms of applicable plans or agreements and is subject to the company’s discretion, consistent with applicable laws. The Company reserves the right to amend or withdraw compensation programs at any time, within the limits of applicable legislation.

Disclaimers: The company is an Equal Opportunity Employer encouraging inclusion in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.