Design Verification Engineer

WHAT YOU DO AT OUR ORGANIZATION CHANGES EVERYTHING

At our organization, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join us, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Person

The ideal candidate would be someone who enjoys working in fast paced environments with emphasis on learning and problem solving. The CIT team designs and verifies cutting edge communication protocol IPs and sub-systems based on the UCIe and UALink standards. As part of the verification team, the candidate will be working on verification methodologies (UVM, Constrained Random Verification, Formal Verification).

Key Responsibilities

• Participate in the verification of complex IP blocks, take end to end ownership of key features for all projects.
• Work on test plans, test case development, testbench enhancement, regression, and coverage closure.
• Deploying industry-leading verification methodologies, such as UVM and Formal Verification.
• Developing testbenches and verification components such as UVCs, models, BFMs, and re-usable verification environments.
• Writing, modifying, and maintaining constraint-random and directed test cases and libraries in System Verilog/UVM.

Preferred Experience

• Extensive hardware verification experience.
• Must be proficient in Verilog, System Verilog, UVM, and working in Linux and Windows environments.
• Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation tools.
• Must have excellent programming skills.
• Must have exposure to Makefile and other scripting languages like Perl, Python and Ruby
• Knowledge of serial communication protocols is a plus.
• Experience with using AI/Machine Learning tools is a plus.
• Familiarity with emulation and post-Si validation is a plus.
• Code line setup, build flow setup, Design/DV automation setup, Regression and Coverage optimization using LSF and cron, Perforce and GitHub - plus

Academic Credentials

Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION: Vancouver, BC

Benefits offered are described: our organization benefits at a glance.

Our organization does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Our organization and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.