Design Verification Engineer

Responsibilities

• Responsible for verification of the ASIC design, architecture, golden models using advanced verification methodologies such as UVM. Write block & top-level tests and debugging fail tests.
• Work with designers to integrate our IP Cores
• Planning and reviewing test plans
• Creating functional coverage points
• Reviewing verification results and metrics and driving the verification convergence towards tape-out
• Run regression.

Qualifications

• MS or BS in Electrical Engineering or Computer Engineering/Science
• Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
• Experience with design and verification tools
• Hands on experience in Perl and Python.
• Some Knowledge of RTL coding (Verilog/VHDL), simulation, synthesis, etc.
• Good oral and written skills for communication and documentation

Highly desirable skills

• Verilog, System Verilog
• Python & Perl programming
• Fast learner

We thank you for your interest, however, only candidates selected for an interview will be contacted.

Our organization is an equal opportunity employer and strives to ensure that its hiring process meets the needs of all persons with disabilities. As such, we will provide reasonable accommodation for any applicant, as requested during the hiring process.