Staff Silicon Design Engineer - RTL Integration

WHAT YOU DO AT AMD CHANGES EVERYTHING

At our organization, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join us, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

The role involves integrating RTL components from different design teams into our next generation FPGA and programmable SOC products; building Full-Chip RTL connectivity models; verifying Full-Chip models match architectural intent; and developing custom tools and methodologies to improve development efficiency and quality.

THE PERSON:

We are looking for a highly qualified and driven RTL digital design engineer to join our FPGA Product Development (FPD) Silicon Integration team. The candidate should have a passion for modern, complex processor architecture, digital design, and verification in general. The candidate must be a team player who has excellent communication skills and experience collaborating with team members and other engineers across globally diverse regions. The candidate must also have strong analytical and problem-solving skills; be willing to learn and ready to take on problems; and is a self-starter able to work on their own as well as within a team.

KEY RESPONSIBILITIES:

• Develop Full-Chip SoC RTL
• Write Full-Chip Design Specification documents
• Work with IP development teams to integrate IP components
• Work across Architecture, Software, and Verification teams to assure Full-Chip SoC RTL quality
• Run lint and other static verification tools
• Generate timing constraints

PREFERRED EXPERIENCE:

• Strong experience using FPGAs and deep understanding of complex FPGA and SoC architectures
• Proven experience in ASIC design flow execution
• Proficient in RTL and behavioral coding in Verilog/SystemVerilog HDL
• Familiarity with CAD tools such as VCS, Verdi, Design Compiler, Primetime, Spyglass, Lint, Conformal, CDC/RDC tools, etc.
• Familiarity in timing constraints for synthesis and STA at SoC level
• Familiarity in Unix/Linux computing environment and scripting languages such as Shell Scripts, Perl, and/or Python
• Familiarity with Revision Control software such as Perforce

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in Computer/Electrical Engineering

LOCATION:

Singapore