STA Design Engineer - ASIC / Low Power

Job Description

The STA Design Engineer will be responsible for conducting complex timing signoff activities and driving closure for next-generation products.

Key Responsibilities

• Perform Static Timing Analysis (STA) and drive timing closure for complex cores and full-chip SOCs.
• Evaluate block-level and top-level timing on gate-level PNR netlists.
• Provide critical feedback to the RTL, Synthesis, and Physical Design teams to improve Power, Performance, and Area (PPA).
• Create and execute Timing Engineering Change Orders (ECOs) to resolve critical timing violations.
• Enhance techniques and methodologies for timing closure and STA flow accuracy to reduce turnaround time (TAT).
• Develop automation scripts (Python, TCL, or Perl) for timing/power data mining and processing.

Key Requirements

• 4+ years of related work experience in Static Timing Analysis.
• Expert proficiency in STA tools such as PrimeTime, PrimeShield, or Tempus for hierarchical analysis in large SoCs.
• Hands-on experience with ECO tools for timing closure.
• Highly proficient in automation scripting using Python, TCL, or Perl.
• Strong knowledge of the complete ASIC design flow (RTL-to-GDS).