Senior Physical Design Engineer

Your Role In Our Mission

At our organization, we’re developing a new thermodynamic computing paradigm to accelerate probabilistic AI workloads by embracing noise, rather than fighting it. Our work combines foundational research on the physics of computing with a mission to ship scalable, reliable silicon and systems to revolutionize AI.

As a physical design engineer, you will work closely with the silicon and hardware R&D team to develop and implement novel thermodynamic computing architectures. You will have significant ownership of chip floorplanning, top-level integration, and signoff, with the goal of delivering reliable silicon and achieving first-silicon-success.

Responsibilities

• You will play a key role in the entire development process of our silicon, from idea to architecture to implementation to tape-out.
• Lead physical implementation of the SOC and all blocks.
• Own key aspects of SOC implementation flow development.
• Perform full chip signoff - including timing checks, power analysis, logical equivalence checking, EM/IR analysis, and physical verification.
• Contribute new ideas for potential thermodynamic computing technology implementations and architectures.
• Floorplan a complex SoC with analog, digital, and mixed-signal blocks.
• Drive requirements for and support analog layouts.
• Participate in the tape-out, bring-up, and testing of our silicon.

What Makes You A Great Fit

• Experience of multiple aspects of SOC implementation through to tapeout - able to discuss personal examples of block layout, IP integration such as padrings, and global clock tree/bus layout.
• Strong familiarity with digital design flows for SOCs.
• Strong understanding of Synthesis, PNR and STA including timing signoff configuration.
• Experienced in configuring decks for, and driving the execution of, physical verification tools from block level to SOC.
• Fluency in Verilog and/or SystemVerilog.
• Experience in scripting languages Python and TCL.
• Excellent communication skills and the ability to work well on a small, interdisciplinary team.

What Elevates Your Application

• Proficiency with the Cadence suite of physical design tools, including Virtuoso, Genus, Innovus, Quantus, Tempus and Voltus.
• Experience mentoring or managing junior engineers.
• Experience with asynchronous logic.
• Experience developing digital design flows.
• Experience with foundries & foundry aggregators to help acquire, set up, and support PDKs, set up and perform LVS and DRC flows, and tape out a completed silicon product.
• Experience selecting, installing and evaluating EDA solutions.
• Experience selecting, sourcing, and integrating third-party IP from multiple different vendors into a silicon product.
• Familiarity with the wafer test, packaging, and chip testing process.
• Experience working at a startup.