HLS Engineer - ASIC / FPGA

HLS Engineer - ASIC / FPGA

We are partnered with a global leader in semiconductors and wireless technology seeking an engineer to join the team developing core digital designs. This role focuses on utilizing High Level Synthesis (HLS) to translate complex algorithms into efficient hardware implementations for both ASIC and FPGA targets, driving optimization for performance, area, and power.

This is a permanent working opportunity based in Cork, Ireland.

Key responsibilities for this HLS Engineer position:

• Take complex, high-level algorithms and translate them into efficient RTL using HLS tools (e.g., Stratus, Catapult, or Vivaldo).
• Decompose sophisticated algorithms into robust, hardware-achievable components.
• Optimize designs for stringent performance, area, and power constraints.
• Guide HLS tools effectively using directives and constraints to achieve desired hardware outcomes.
• Develop and execute verification test benches for HLS-generated designs.
• Collaborate with RTL designers to ensure smooth integration of HLS-generated modules into the overall architecture.
• Participate in hardware bring-up and debugging.

Key requirements:

• 2+ years of experience in digital design, RTL design (Verilog/SystemVerilog), or FPGA design.
• Extensive experience with high-level programming languages like C/C++.
• Hands-on experience with HLS tools for ASIC or FPGA design (e.g., Stratus, Catapult, or Vivaldo).
• Strong knowledge of basic processor architecture.
• Solid understanding of HLS concepts such as scheduling, resource allocation, pipelining, and optimization techniques.
• Proficiency in scripting with Python or TCL is a strong plus.

Keywords: High Level Synthesis / HLS Engineer / ASIC / FPGA / C++ / Digital Design / RTL / Verilog / SystemVerilog / Stratus / Catapult / Vivaldo / Hardware Optimization / Performance / Area / Power / Pipelining / Hardware Verification / Debugging / Semiconductor