Entry Level Design, Verification, and Validation Engineers - December 2025 and May 2026 Grads

Job Description

Design, Verification, and Validation Engineers play an important role in developing products across all Business Lines. Opportunities are available in both Digital and Analog Design, as well as Functional Verification, and Validation. Business Lines hiring include MCU/MPU, Automotive Processing, Edge Processing, Connectivity & Security.

As a design engineer, you would be involved in the entire activity around the design for your project. You take ownership of the RTL design at block level and contribute through various phases of the ASIC/SOC design process.

Verification Engineers may work with state of the art mixed signal ICs with experience in UVM or OVM. Responsibilities include architecting verification strategies, participating on a team to verify logic designs, and building System Verilog constraint driven testbenches.

The organization has rejuvenated its analog focus bringing to market new, innovative products that combine analog and mixed signal capability with embedded control for automotive body, radar, chassis and safety, powertrain and driver information systems. On the consumer side, we provide highly integrated power management ICs for portable communications and computing products such as tablets, slates, e-readers and netbooks.

• Perform functional simulations and design debug
• Develop functional verification plans
• Develop functional verification testcases, Verification IP, and testbench components
• Develop scripts and automation to enhance coverage reports
• Perform digital silicon validation using development boards and lab equipment
• Development of validation infrastructure, test case development for validation targeted for an IP, sub-system, or SoC level.
• Develop digital validation plans
• Develop digital validation testcases, and debug silicon, as required
• Develop scripts and automation to enhance coverage reports
• Create and execute test plan for the function of design
• Design, implement, and improve UVM test bench.
• Run coverage and regression. Analyze coverage gaps and devise strategy to achieve higher code coverage.
• Develop and refine test cases and simulation model.
• Work closely with different functional groups to support successful product release.

BS or MS in Electrical Engineering, Computer Engineering, Computer Science or similar is required, along with up to 2 years experience, including internships.

Experience or coursework in the following are helpful in determining which product or business line you might support:

• Logic / digital design.
• Digital verification using System Verilog and UVM methodology.
• Mixed-signal IC design
• Understanding of digital and mixed-signal debug
• Any experience with EDA tools desirable.
• Scripting in Python, Perl, TCL,
• Embedded code development (C, Assembly)
• OOPS, C/C++ software development
• ASIC/SOC design flow
• Hands-on RTL coding is a big plus
• Hands-on experience in lab, and familiar with lab equipment
• Post silicon logic debug background, analyzing test logs, SW hooks development for debug purposes
• Excellent debugging skills and drive to develop innovative hardware.
• Strong critical thinking, problem solving
• Strong written and oral communication skills