Design Verification Engineer

Job Description

Join our organization as a Design Verification Engineer to help verify complex low-latency FPGA systems. Be part of a team at the forefront of innovation in design verification.

Responsibilities

• Design and maintain robust testbenches and targeted tests using a mixed open-source and proprietary verification environment.
• Develop and own comprehensive verification plans, ensuring coverage goals and test strategies are clear and defensible.
• Identify and diagnose RTL issues quickly, working directly with designers to accelerate bring-up and resolve design defects efficiently.
• Oversee and refine the test infrastructure, including management of test suites, CI pipelines, and the improvement of both internal and open-source tooling.

Requirements

• Strong debugging and analytical capability, able to isolate and resolve complex RTL and testbench issues efficiently.
• At least two years of professional RTL functional verification experience for FPGA or ASIC designs.
• Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis.
• Proficiency in Python and/or C++ for building verification infrastructure, tooling, and automation.