ASIC Digital Design, Sr Staff Engineer - Verification

Global-Talent-Exchange

Ho Chi Minh City
Full time
8 - 10 Yrs
Job Openings: 1

Required Skills:

Design Verification

Simulation Tools

Scripting Languages

SystemVerilog

Formal Verification

UPF

UVM

SVA

Perl

TCL

Python

ASIC Digital Design

Design Verification

Simulation Tools

Scripting Languages

Advanced Verification Techniques

Digital and Mixed-Signal Designs

SystemVerilog

VCS/Verdi

Formal Verification

UPF

UVM

SVA

Perl

TCL

Python

Job Description

We are seeking a passionate and experienced ASIC Digital Design Engineer with a strong background in design verification. The ideal candidate thrives in a collaborative environment and has a keen eye for detail. With a minimum of 8 years of experience in design verification, you will have honed your skills in using simulation tools, scripting languages, and advanced verification techniques. You will contribute to cutting-edge technologies that enable Data Center, AI/ML, and 5G applications.

Responsibilities

  • Work in a Digital and Verification Development team during the development and validation of complex digital mixed signals for high-speed interface IP.
  • Plan tests, checklists, coverage, and assertion planning.
  • Create detailed verification environments from functional specifications.
  • Apply advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.
  • Write test cases, checkers, and coverage that implement the verification test plan.
  • Debug simulations, including those of real signals modeled using SystemVerilog for analog.
  • Perform RTL, GLS, and co-simulations and ensure coverage closure.
  • Participate in technical reviews and contribute actively.
  • Provide customer support with the bring-up of IP in customer simulation environments.
  • Follow and improve development processes to ensure high-quality output.

Qualifications

  • BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
  • 8+ years of experience in design verification.
  • Strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal).
  • Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus.
  • Proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.
  • Excellent English communication skills, both verbal and written.
  • A great team player, willing to support others.
  • Self-motivated and highly enthusiastic about technology and solving problems.

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