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Responsibilities And Tasks

• Promote worldwide synergy for improved benchmark performance and efficiency gains through global project management and execution, network BKM leveraging and enhancement, and business process creation and re-engineering.
• Define strategies to ensure that Packaging Technology and interaction with Front End manufacturing process are fully developed and qualified well ahead of any qualification of the product itself.
• Lead the PI Loop taskforce and/or team in network to address yield and quality challenges, optimize process flow in a timely manner to achieve BIC yield performance.
• Maintain and enhance domain knowledge and technical expertise, explore innovation opportunities with strategic thinking and systematic approach.
• Maintain a strong and open relationship with peer group and managers in other functional areas within central team and outside in areas such as Fab, TD, Product Engineering, GQ. Communicate and respond to issues in a timely manner. Help drive to fix the issue where necessary.
• Demonstrate ability to give effective presentations to both small and large groups on project updates and new initiative proposals.
• Periodically follow up with manager to ensure all type of goals are met and get assistance to remove obstacles.
• Travel to Micron Fab locations as necessary for face-to-face work.

Requirements

• Knowledge in Semiconductor Device Physics, DRAM operations, wafer fabrication process flows, parametric/electrical test and probe yield.
• The experience on DRAM HPM, BEOL integration, advanced packaging and layout will be a plus to this job position.
• Good data analysis, troubleshoot, problem solving, reporting and presentation skills with a strong attention to detail.
• Good multi-tasking, verbal, and written communication skills.
• Strong interpersonal skills and customer/co-worker relationships. Successfully demonstrated teamwork skills with a strong focus on developing good team dynamics.
• Good organizational capabilities and ability to work effectively with minimal supervision.
• Intermediate to advanced PC skills including Microsoft Office.
• Ability to be flexible with job responsibilities and take the initiative to assume added responsibilities.
• Travel Required: Yes. Willing to travel as needed to support department goals
• Travel Frequency: 20-50%.

Education

• Bachelor’s or Master's degree in Electrical Engineering, Microelectronics, Physics, Chemistry, Material Science Engineering or related field.

Job Description

As a PLC Engineer, you will be responsible for minimizing downtime through onsite intervention. Your role will involve triaging, diagnosing, and resolving system errors, faults, and disruptions. Excellent communication skills are essential due to frequent customer contact. A problem-solving mindset with strong analytical skills is required to translate customer needs into technical solutions.

Job Responsibilities

• Support Low-Level-Control systems and address PLC issues raised by the operations and maintenance team.
• Diagnose and rectify Low-Level-Controls and PLC faults within tight deadlines.
• Program, troubleshoot, and repair sensors, scanners, visualization systems, motors, frequency inverters, and encoders.
• Coordinate controls design with other engineering disciplines and project management.
• Provide technical support for root cause analysis related to control system issues and failures.
• Drive continuous improvement through enhancements to existing control software and hardware systems.
• Conduct orientation and training for staff and external users.

Job Requirements

• Bachelor’s degree in Mechatronics, Electrical Engineering, Software, or Industrial Automation.
• Relevant working experience with Operational Technology and Siemens PLC during commissioning, installing, and debugging in an international environment.
• 3-6 years of relevant experience in the automation industry control system.
• Proficient in Siemens-S7 programming, TIA Portal, Distributed Safety, RSLogix, and OMRON.
• Working knowledge of communication protocols and troubleshooting skills.
• Working knowledge of Control net, Profibus, Profinet, and AS-I bus is an advantage.
• Working knowledge of Variable Frequency drives.
• 24x7 support may be required for critical situations, and participation in weekend stand-by duties may be necessary.

Job Description

About the Job

• Lead and execute validation projects for computerized and automation systems in compliance with GxP and other relevant regulatory standards.
• Develop, review, and maintain CSV standards, procedures, and guidance for lifecycle management.
• Author and review validation documentation, including validation plans, protocols, reports, traceability matrices, and risk assessments.
• Provide expert consultation and oversight to ensure compliance with regulatory requirements (e.g., GAMP 5, FDA 21 CFR Part 11, Annex 11).
• Collaborate with cross-functional teams (IT, Quality, Engineering, Operations) to plan and implement validation activities.
• Drive continuous improvement of validation processes, governance, and best practices.
• Make independent decisions related to validation strategy, execution, and deliverable approval.
• Support internal and external audits, ensuring inspection readiness and compliance alignment.

About You

• Academic background: engineering, life sciences, or related field
• 8–10 years of experience in Computer Systems Validation (CSV), Automation, or related quality and compliance roles within a regulated environment (pharmaceutical, biotech, or manufacturing preferred).
• Ability to lead projects from planning through execution and reporting, managing stakeholders and deliverables effectively.
• Prior experience in Rockwell Building Automation System (BAS) upgrades is highly preferred.
• Must be able to work independently, manage multiple priorities, and deliver results under minimal supervision.
• Demonstrated ability to make informed decisions and generate deliverables for system validation in a compliant and timely manner.
• Strong knowledge of regulatory frameworks (GxP, FDA 21 CFR Part 11, EU Annex 11) and validation lifecycle approaches (GAMP 5).
• Excellent analytical, problem-solving, and documentation skills.
• Strong communication and stakeholder management abilities across cross-functional and technical teams.

Why Join Us?

• Global Diversity: Be part of an international team of 110+ nationalities, celebrating diverse perspectives and collaboration.
• Trust and Growth: With 70% of our leaders starting at entry-level, we’re committed to nurturing talent and empowering you to reach new heights.
• Continuous Learning: Unlock your full potential with our internal Academy and over 250 training modules designed for your professional growth.
• Vibrant Culture: Enjoy a workplace where energy, fun, and camaraderie come together through regular afterworks, team-building events, and more.
• Meaningful Impact: Join us in making a difference through our CSR initiatives, including the WeCare Together program, and be part of something bigger.

Responsibilities

• Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification
• Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance
• Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels
• Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out
• Work with design engineers to debug and identify root causes of simulation failure
• Support test engineers for post-silicon validation
• Mentor and coach team members and junior engineers. Drive verification efficiency

Requirements

• MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree
• In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology
• Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and testcases development for function/performance verification
• Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding
• Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core
• Experience in verifying designs at both of RTL level and post-P&R gate level
• Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team

Experience in one or more of the following areas considered a strong plus:

• Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators
• Experience in verifying mix-signal design and interface of digital and analog
• Experience of design verification for highspeed IO such as PCIE and DDR

Job Responsibilities

The team is responsible for driving innovation by designing, developing, and producing CPUs for data center servers. The focus is on creating high-performance, energy-efficient, and reliable chips for a wide range of electronic devices and systems.

• Lead analog design of complex IPs for SoC.
• Determine the best solution for the product.
• Conduct design from definition to product in advanced process nodes.
• Design components such as PLL, ADC/DAC, DC/DC, LDO, Amplifier, Reference generator, Temp sensor, Voltage monitor, and Power detector.

Qualifications

Minimum Qualifications

• MS or PhD degree in Electrical Engineering or equivalent practical experience.
• 5 years of experience in analog/mixed signal design.
• Experience in modeling and simulating complex systems.
• Experience in IP design, including PLL, DC/DC, LDO, Bandgap, Amplifier, ADC/DAC.
• Experience with Cadence design tool.
• Ability to supervise layout.

Preferred Qualifications

• Solid knowledge of device physics.
• Understanding of CPU environment and need for analog IPs.