Staff Verification Engineer - Silicon Design

Global-Talent-Exchange

Singapore

Full time

5 - 8 Yrs

Job Openings: 1

Required Skills:

SystemVerilog

Uvm Environment

C/C++ STL

Python

Perl

SystemVerilog

UVM

C/C++

Python

Perl

WHAT YOU DO AT THE COMPANY CHANGES EVERYTHING

At our organization, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join us, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

We are looking for an experienced Verification Engineer to join our team for cutting-edge server memory products. This individual will be responsible for driving the verification efforts of DDR interfaces, including advanced memory protocols such as DFI, DDR5, and LPDDR5/LPDDR6, across a range of DIMMs (Dual In-line Memory Modules). The ideal candidate will possess advanced knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python/Perl.

The Person

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

Key Responsibilities

Work with a team of verification engineers in the development and execution of verification plan for DDR5, LPDDR5, and DFI memory systems in server products.
Comprehend the PHY's interaction in the complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features of the memory interface.
Understand RTL and micro-architecture sufficiently to engage in cross functional discussions with IP/Domain architects and Design engineers for planning and debug.
Knowledge sharing and other contributions to verification methodology.
Support Post-Si teams for Product Performance, Power and functional issues debug/resolution.

Preferred Experience

Developed and implemented SystemVerilog and UVM (Universal Verification Methodology) based testbenches, simulation environments, and functional coverage models for DDR5 and LPDDR5 systems.
Worked closely with hardware, firmware, and software teams to align on system-level memory architecture, identify potential integration issues, and define validation requirements early in the design phase.
Built VIPs and BFMs for memory interfaces from scratch (preferable).
GLS, NLP, XPROP simulation experience is preferable.
Strong proficiency in system verilog assertions, constraints and coverage.
Worked in formal verification methods, with proven record of tool usage beyond the standard apps.
Excellent communication, management, and presentation skills.

Academic Credentials

Bachelor’s or Master’s degree in related discipline.

LOCATION:

Singapore

Benefits offered are described: our organization benefits at a glance.Our organization does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. We and our subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.Our organization may use Artificial Intelligence to help screen, assess or select applicants for this position. Our “Responsible AI Policy” is available here.This posting is for an existing vacancy.