STA Design Engineer

We are currently supporting the hiring process for a leading semiconductor company developing advanced high-performance, low-power ASIC and SoC technologies used across mobile, compute, and next-generation connected platforms.

Our client is seeking an experienced Static Timing Analysis (STA) Engineer to join a highly collaborative engineering team focused on timing signoff, methodology development, and timing closure for complex cores and full-chip SoCs.

In this role, you will work closely with RTL, Synthesis, Physical Design, and architecture teams to ensure timing convergence and optimal PPA across advanced semiconductor products. You will contribute to the development of robust timing methodologies, automation flows, and ECO strategies that support world-class silicon execution.

Key Responsibilities

• Perform static timing analysis and timing closure for complex cores and full-chip SoCs
• Analyze gate-level netlists and provide timing feedback to RTL, Synthesis, and Physical Design teams
• Develop and maintain timing constraints and signoff methodologies
• Drive improvements in timing closure accuracy, turnaround time, and flow efficiency
• Generate and implement timing ECOs to resolve setup/hold violations
• Ensure compliance with timing signoff criteria and verification checklists
• Develop automation solutions for timing and power data analysis using scripting languages
• Support project execution through collaboration with cross-functional engineering teams
• Troubleshoot and resolve timing-related issues throughout the development lifecycle

Required Skills & Experience

• Strong expertise in STA tools such as PrimeTime, PrimeShield, or Tempus
• Hands-on experience with timing closure and ECO tools including Tweaker, PrimeClosure, PTECO, or Tempus ECO
• Strong understanding of ASIC design flows from RTL-to-GDS
• Proficiency in automation and scripting using Python, TCL, or Perl
• Experience working on large hierarchical SoC designs
• Strong debugging, analytical, and problem-solving skills
• Ability to work effectively in fast-paced, cross-functional engineering environments
• Excellent communication and collaboration skills

Preferred Experience

• Exposure to Design for Parametric Yield methodologies
• Familiarity with extraction and circuit simulation environments
• Experience improving timing methodologies and signoff flows
• Knowledge of low-power design and PPA optimization techniques

Qualifications

• Bachelor’s or Master’s degree in Electronics, Computer Engineering, Computer Science, or a related discipline
• 4+ years of relevant industry experience in STA, timing closure, or ASIC implementation

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