Design Verification Engineer

WHAT YOU DO AT OUR ORGANIZATION CHANGES EVERYTHING

At our organization, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join us, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

DESIGN VERIFICATION ENGINEER

The Role

We are looking for motivated individuals seeking opportunities to solve complex problems in a fast-paced work environment. The successful candidate will be involved in all aspects of our next generation products. This includes verifying PCI Express designs using the latest UVM standard and developing a comprehensive test plan to ensure coverage closure. The position allows exposure to all aspects of ASIC design stages.

The Person

• Creative innovator and thinker who loves technical problems and detail-oriented tasks
• Exhibits relentless commitment to help the team meet quality and development goals on schedule
• Drives to learn and perform at their highest potential in a technical capacity
• Thrives in both a team environment and in individual contribution
• Communicates openly and clearly in meetings, presentations, emails, and reports
• Able to learn independently and acquire new skills required for the job
• Flexible in working hours to accommodate working with co-workers in different time-zones

Key Responsibilities

• Writing/Implementing/Reviewing Test Plans
• Developing Testbenches and Verification Components such as UVCs, models, BFMs, and Re-usable Verification Environments
• Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries in System Verilog/UVM
• Analyzing Functional, Code, and Test Plan Coverage
• Implementing Assertions, Checkers, and Monitors
• Utilizing In-House and 3rd Party IP/SOC CAD and EDA Tools for Design Verification
• Deploying Industry-Leading Verification Methodologies such as UVM
• Triaging and Debugging Regressions
• Reproducing Functional Bugs found in Silicon in Simulation Verification tools
• Conducting and participating in Code Reviews
• Technical leadership is an asset, including driving projects from start to the finish and design verification sign-off

Preferred Experience

• Testbench Architecture, System Verilog, UVM
• Digital Design in RTL, Verilog HDL
• C/C++, Java, or other object-oriented programming language
• Perl, Ruby, Shell-scripting, UNIX/LINUX Environment
• VCS, NCSIM, Questa, or other simulator and associated waveform viewers such as Verdi
• PC System Architecture: PCI Express, x86, ARM
• On-Chip Bus Interfaces and Architectures: AMBA AXI, OCP, PIPE

Academic Credentials

• Masters or Bachelor degree with working experience in ASIC area

LOCATION:

Vancouver, British Columbia