IP/SoC Design - Sr Engineer/Lead
Loom International
Required Skills:
micro-architecture
Digital Design
RTL development
Verilog
Synthesis
DFT
verification
formal verification
silicon debug
Lint
CDC
CLP
IP/SoC design
micro-architecture
interconnect protocols
Digital Design
RTL development
Verilog
ARMv8/v9 CPU architecture
Synthesis
DFT
verification
formal verification
silicon debug
Lint
CDC
PLDRC
CLP
General Summary
Minimum Qualifications:- 2 to 8+ years of solid experience in IP/SoC design and micro-architecture
- Understanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts
- Good knowledge of Digital Design and RTL development
- Hands-on experience with SoC Design, Verilog RTL coding
- Understanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization.
- Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debug
- Working knowledge of Lint, CDC, PLDRC, CLP etc
- Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification
- Manage SoC dependencies, planning and tracking of all front-end design related tasks
- Driving project milestones across the design, verification and physical implementations
- Should possess effective communication and leadership skills
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
Minimum requirement is Bachelor of Engineering
Preferred is Masters of Engineering in Computer Science or Computer Engineering. PhD in Computer Science, Engineering, Information Systems, or related field