DFT Lead (Design for Testability Lead)
Cyient
Hyderabad
Full time
6 - 11 Yrs
- INR
Job Openings: 1
Required Skills:
DFT
Chip Design
Hiring For  DFT Lead at Hyderabad

Job Title: DFT Lead
Job Type: Full Time Permanent Job
Location: Preference is Hyderabad first, 2nd priority can be Bangalore


Required Skills:
Experience with Synopsys tools are required. Must have 6+ years of DFT Experience.
We are looking for Immediate joiners

Job Description:
  • Should have worked hands-on extensively on full chip DFT design, implementation, vector generation/verification, JTAG, boundary scan and simulation.
  • Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus.
  • Should have participated in successful tapeouts ofSoC/ASIC chips at 14nm or below and achieved test targets.
  • Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA.
  • Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process.
  • Excellent problem solving and debugging skills. Proactive in nature
  • Leading junior teams, Mentoring/Training and Project leadership.
  • Excellent Customer interaction, Communication and Teamwork skills.

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Best, 
Vijay Kumar
Sr. Technical Recruiter | Global Talent Exchange
Mobile: +91 9121673676
About Company
Cyient
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