Roles and Responsibilities:

Looking for an experienced senior verification engineer with > 10 years of experience in ASIC/SOC/IP/block level functional verification using system verilog/UVM.
The ideal candidate will have strong command of UVM, advanced UVM and system Verilog

Key responsibilities:

Develop a comprehensive test plan, complete test-bench and robust verification environment including interface agents and scoreboard in UVM
possess deep knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB, NVMe or similar
Strong debugging skills to address TB issues quickly and test failures.
Take responsibility for verification closure by addressing coverage and managing bug reports
proficiency in using industry standard verification tools such as Questa, VCS or Model Sim
Experience with scripting languages like python, Perl or TCL for automation tasks

Manage a team of 6 to 7 Engg, Interact with the customer on the tasks and status updates 

Mandatory Skills:

Scripting Languages, System Verilog, Functional Verification, Test Bench, Verilog, Perl Programming, Design Verification, PCIe

Desirable Skills:

Scripting Languages, System Verilog, Functional Verification, Test Bench, Verilog, Perl Programming, Design Verification, PCIe