Company Overview

At Maieutic, we are building cutting-edge AI tools for chip designers to streamline workflows, boost productivity, and accelerate innovation. Founded by successful entrepreneurs and second-time founders with 75+ patents to their name, we bring deep expertise in semiconductor design, AI, and automation to tackle the industry's toughest challenges.

Backed by marquee investors, we are well-positioned to drive the next wave of innovation in semiconductor design. Our mission is to empower designers with intelligent assistants that act as both productivity enhancers and innovation catalysts, ensuring faster design cycles, smarter decisions, and higher efficiency in the ever-evolving semiconductor industry.

We are assembling a world-class AI and full-stack development team based in Bangalore, India. If you're passionate about AI, full-stack development, and keen to work on game- changing technology, we would like to hear from you! Reach out to hr@maieuticsemi.com

We are an equal opportunity employer and value diversity. All qualified applicants will receive consideration for employment without regard to race, religion, gender, sexual orientation, age, disability, or any other protected status.

Senior EDA Engineer – Cadence Virtuoso, SKILL/CDF, Tool Integration

Role Overview:

We are seeking a highly skilled EDA Engineer with solid experience in Cadence Virtuoso environments and a deep understanding of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and schematic/layout tool automation. This role will collaborate closely with AI/EDA development teams to build seamless design flows and robust automation for our AI-powered analog design platform.

Key Responsibilities:

·       Develop, maintain, and optimize analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools.

·       Create, modify, and optimize SKILL scripts for automation of layout, schematic, verification, and design environment tasks.

·       Manage Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries.

·       Work extensively with the OpenAccess (OA) database API (using C++, Python, Tcl) to read, write, and manipulate design data including schematic, layout, connectivity, and library information.

·       Develop automation tools and workflows leveraging OpenAccess to integrate schematic and layout views, support PDK/CDK validation, and assist design data migration or QA.

·       Integrate and validate foundry PDK/CDK devices, parameterized cells (pCells), symbols, DRC/LVS decks, and simulation models with EDA tools.

·       Troubleshoot issues related to PDK integration, OA database consistency, schematic-layout synchronization, and environment setups.

·       Document technical processes, create reusable automation scripts, and contribute to team best practices.

·       Collaborate with AI and software teams to integrate EDA tools into Maieutic’s AI co- pilot platform and support continuous improvement of design automation.

Required Skills s Experience:

·       3–8 years hands-on experience working with Cadence Virtuoso analog/mixed-signal design flows.

·       Strong proficiency in SKILL scripting for automation within Cadence layout and schematic environments.

·       Proven experience managing and customizing CDF files for parametric device libraries in Cadence.

·       Hands-on experience with OpenAccess (OA) database API: Familiarity with OA schema, ability to program in C++, Python, or Tcl to develop tools/scripts that access and modify OA layout and schematic data.

·       Deep understanding of foundry PDK/CDK structures, including parameterized cells, symbols, device models, layout generators, and associated design-rule decks.

·       Experience automating schematic and library processes using scripting languages (SKILL, Tcl, Python).

·       Solid knowledge of schematic editors/viewers and maintaining schematic-layout synchronization (LVS/Schematic Driven Layout).

·       Strong UNIX/Linux command-line skills and scripting abilities.

·       Experience with version control systems/tools used in EDA environments (Git, SOS, or equivalent).

·       Excellent communication skills and ability to operate effectively in a startup team environment.

Preferred Qualifications:

·       Previous work experience at Cadence or semiconductor companies specializing in Virtuoso toolchains.

·       Experience with Spectre, ADE simulation, and analog verification flows.

·       Understanding of semiconductor process technology and device physics applicable to analog/mixed-signal design.

·       Familiarity with AI/ML integration in design tools is a plus.

Maieutic Semiconductors

Company Overview

At Maieutic, we are building cutting-edge AI tools for chip designers to streamline workflows, boost productivity, and accelerate innovation. Founded by successful entrepreneurs and second-time founders with 75+ patents to their name, we bring deep expertise in semiconductor design, AI, and automation to tackle the industry's toughest challenges.

Backed by marquee investors, we are well-positioned to drive the next wave of innovation in semiconductor design. Our mission is to empower designers with intelligent assistants that act as both productivity enhancers and innovation catalysts, ensuring faster design cycles, smarter decisions, and higher efficiency in the ever-evolving semiconductor industry.

We are assembling a world-class AI and full-stack development team based in Bangalore, India. If you're passionate about AI, full-stack development, and keen to work on game-changing technology, we would like to hear from you! Reach out to hr@maieuticsemi.com

AI/ ML Engineer

Position Overview

We are seeking a skilled AI/ML Engineer with expertise in developing and deploying classical machine learning models for image/time series data and building agentic workflow with Large Language Models.

Required Skills & Qualification

•                Strong understanding of deep learning concepts, including transformers, attention mechanisms, and transfer learning.

•                Developing and debugging machine learning models using Python and ML libraries (TensorFlow, PyTorch).

•                Expertise in Graph Neural Networks is a plus.

•                Expertise in Large Language Models - prompt engineering and agentic workflow - is a plus.

•                4+ years' experience, Mathematics, Computer Science or Electronics degree required.

Key Responsibilities

•                Preparing datasets from unstructured data in papers/books/internet by extracting images, text, and tables.

•                Develop knowledge graphs from unstructured data.

•                Apply data augmentation and synthetic data generation techniques to enhance model performance.

•                Developing agentic workflow around LLMs.

•                Preparing evaluation frameworks for LLMs for consistency.

•                Deployment of Large Language Models in on-premises environments.

Location: Bangalore (On-site)

Employment Type: Full-time

Experience: 5 to 10